1. Field of the Invention
The present invention relates to a channel equalizer, in particular to a real/complex dual combination channel equalizer which is capable of minimizing complexity of the channel equalizer by owning resources constructing the real/complex channel equalizer jointly to the maximum while maintaining performance of each mode.
2. Description of the Prior Art
In general, a channel equalizer is for reducing bit detection error by compensating distortion occurred through band-width limited by a plurality of filters used for a transmission/reception terminal and multipath of a transmission channel when a signal is transmitted/received on a digital transmission system such as a high picture quality TV.
Particularly, when a signal transmitted from a transmission terminal is distorted and noise is included, error occurrence probability of a signal received to a reception terminal increases in proportion to increase of a signal level, accordingly a channel equalizer is used on the reception terminal in order to reduce the error occurrence probability by compensating distortion of the received signal.
The channel equalizer is divided into a real channel equalizer and a complex channel equalizer in accordance with a transmission method. The real channel equalizer transmits a transmission signal by putting it on a real channel such as a terrestrial VSB (Vestigial Side band) transmission method.
The complex channel equalizer transmits a signal by putting it separately on a real channel and an imaginary channel such as a cable, a QAM (Quadrature Amplitude Modulation) and a QPSK (Quadrature Phase Shift Keying) transmission method.
However, there are various transmission methods in the present times, a receiver which is capable of operating not the terrestrial or cable transmission method but both methods is required, accordingly the channel equalizer has to compensate distortion of a signal received by the both transmission methods.
The real channel equalizer and complex channel equalizer will now be described as below.
FIG. 1 is a block diagram illustrating a construction of a general real channel equalizer. It comprises a delaying unit 105 for delaying orderly digital data inputted from outside, a multiplying unit 103 for multiplying each tap coefficient Coef to the data outputted from the delaying unit 105, an adding unit 100 for adding a value outputted from the multiplying unit 103 and outputting it, an adder 101 for adding a value outputted from the adding unit 100 to a value outputted from a decision orientation filter unit 106 and outputting equalization data, a determining unit 102 for outputting decision data by the value outputted from the adder 101, a subtracter 104 for finding difference between the value outputted from the determining unit 102 and value outputted from the adder 101 and outputting an error value, a decision orientation filter unit 106 for being inputted the error value of the subtracter 104 and the decision data value outputted from the determining unit 102 and outputting it by performing decision orientation filtering, a multiplier 109 for multiplying the error value outputted from the subtracter 104 to the input data and outputting a step magnitude μ, and an adder 107 for renewing the tap coefficient by the step magnitude outputted from the adder.
The operation of the real channel equalizer will now be described as below.
When the digital data outputted from the transmitter is inputted to the real channel equalizer, the delaying unit 105 passes the inputted digital data orderly to a delayer as same as the number of the number of the tap, and outputs the each delayed data to the multiplying unit 103. The multiplying unit 103 multiples the tap coefficient Coef. to the inputted digital data and the each delayed signal and outputs it. The adding unit 100 adds the outputted each data, and outputs it. The first subtracter 101 subtracts the outputted data and the data outputted from the decision orientation filter unit 106, and outputs it to the determining nit 102. The determining unit 102 outputs data determined by the inputted data. The second subtracter 104 subtracts the determined data and the data subtracted in the first subtracter 101, and yields an error value of the inputted data. The adder 109 yields magnitude of the step by multiplying the yielded error value to the input data. The adder 107 yields a value which renews the tap coefficient by the step magnitude, and outputs it to the multiplying unit 103. The error decreases by compensating distortion of the received data.
FIG. 2 is a block diagram illustrating a construction of a general complex channel equalizer. The construction of the complex channel equalizer is similar to the construction of the real channel equalizer, however algorithm about an imaginary part is added.
The construction of the complex channel equalizer will now be described as below. The complex channel equalizer comprises a real data processing unit for processing real data and an imaginary data processing unit for processing inputted imaginary data.
First, the real data processing unit will now be described. It comprises a delaying unit 205 for delaying the inputted real data orderly, a first operation unit 201 for multiplying a real tap coefficient Real Cpef. to the each delayed data, adding the real tap coefficient added data, and outputting it, a second operation unit 206 for adding separately an imaginary coefficient Imaginary Coef. to the each delayed data, outputting it, and adding the each data, a first subtracter 202 for subtracting the data outputted from the first operation unit 201 from the data outputted from a third operation unit 208, a second subtracter 203 for outputting equalization data by subtracting the data outputted form the subtracter 202 from the data outputted from a real decision orientation filter unit 207, a real determining unit 204 for outputting decision data and a real error value by the data outputted from the second subtracter 203, and a real decision orientation filter unit 207 for being inputted the error value and the decision data value outputted from the real determining unit 204, and performing a decision orientation filtering.
Meanwhile, the construction of the imaginary data processing unit is same with the construction of the real data processing unit. It comprises a delaying unit 212 for delaying the inputted imaginary data orderly, a third operation unit 208 for multiplying an imaginary tap coefficient Real Coef. to the each delayed data and inputted imaginary data, a fourth operation unit 213 for multiplying the real coefficient Real Coef. to the each delayed data and inputted imaginary data, an adder 209 for adding the data outputted from the fourth operation unit to the data outputted from the second operation unit 206, a subtracter 210 for subtracting the data outputted from the adder from the data outputted from an imaginary decision orientation filter unit 214, an imaginary determining unit 211 for outputting decision data value and an error value from the data outputted from the subtracter 210, and the imaginary decision orientation filter unit 214 for being inputted the error value and the decision data value, and performing a decision orientation filtering.
The part renewing the tap coefficient in the above-described complex equalizer will now be described with reference to accompanying FIG. 3.
FIG. 3 is a block diagram illustrating a construction of the tap coefficient renewing part of a general complex channel equalizer. It is constructed with a first and second multipliers 301, 307 for multiplying separately the real data to the error values outputted from the real determining unit 204 and imaginary determining unit 211, a third and fourth multiplier 308, 311 for multiplying separately the imaginary data to the error values outputted from the real determining unit 204 and imaginary determining unit 211, a subtracter 302 for subtracting the value outputted from the first and third multipliers 301, 308, an adder 304 for renewing the tap coefficient of the real data by the magnitude of the step calculated by the subtracted data value, an adder 312 for adding the value of the second and fourth multipliers 307, 311, and a summing amplifier 314 for renewing the tap coefficient of the imaginary data by the magnitude of the step calculated by the added data value.
The operation of the complex channel equalizer is same with the operation of the above-described channel equalizer, accordingly its description will now be abridged.
The construction of the real and complex channel equalizers are similar each other. However, generally the real channel equalizer needs 1 tap filter in order to calculate an output of a filter value of each terminal, and the complex channel equalizer needs 4 taps in order to calculate an output of a filter value of each terminal.
Accordingly, when the complex channel equalizer operates in a real mode, it is impossible to use 3 taps filter on the each terminal, when the real channel equalizer operates in a complex mode, a ghost more far than in a cable use occurs due to influence of an multiplath. In order to compensate the occurred ghost, filter taps of lots of terminals are required, accordingly, the construction of the receiver is complicated.
In addition, when the real/complex channel equalizer is designed independently to the receiver so as to be appropriate to the various transmission methods, the overall construction of the receiver is complicated, and the volume of the receiver increases.